As technology advances, electronic devices become smaller, and this raises requirements for electronic packaging technology and assembly quality. A variety of new packaging technologies are gradually being developed, and recently new industries for electronic packaging have appeared.
The electronic packaging is to protect electronic devices and circuits from influences in the external environment, which includes physical and chemical influences. That is, it isolates the external environment using a protective layer to protect the electronic devices. The electronic packaging means a manufacturing process that a variety of electronic devices are assembled and connected on demand when producing electronic apparatuses. The electronic packaging has the effect of power distribution, signal distribution, heat dissipation, protective packaging and enhancement of mechanical strength of the apparatus, and furthermore physical and electric connections of circuits and systems in electronic devices. The types of electronic packaging may be classified into metal packages, ceramic packages and plastic packages according to the material; pre-mold packages and post-mold packages according to the technique; and Single Inline Package (SIP), Dual Inline Package (DIP), Plastic Leaded Chip Carrier (PLCC), Quad Flat No Leads (QFP), Chip-Size Package (CSP), etc. according to the package housing.
The present invention is a packaging technology applicable to an electronic device, wherein the processes for the electronic package may be classified into level 1 to 4 packages. Level 1 package is a process to assemble an exposed IC chip to form a first electronic device and cause the IC to have I/Os using an assembly method. The assembly method includes Wire Bonding, Flip Chip, Tape Automatic Bonding, etc. Level 2 package is a process to adhere the first electronic device to a first substrate (e.g., PCB) to form a second electronic device. The adhering methods include Pin Through Hole (PTH) and Surface Mount Technology (SMT). Level 3 package is a process to assemble a second substrate having a plurality of second electronic devices on a motherboard to form a subsystem. Level 4 package is a process to combine subsystems to form a complete electronic product. Objectives of each level of packaging include higher efficiency, smaller size, and lower cost.
Because SMT technology needs no through holes corresponding to the pins of the electronic device, and the size of the electronic device which uses SMT technology is smaller than which uses through-hole package, SMT technology has inevitably become the main technology for more functional and smaller electronic devices.
The packaging process of SMT technology includes solder-paste printing, component placement, and reflow processes. The processes involve very complicated and extensive factors, such as original materials, machinery equipment, parameter setting, production process, and so on. Wherein, the component placement technique involves a dispensing technique and a dot control technique. It is a challenge for one skilled in the art how to stably and efficiently produce high-quality electronic products. The research has revealed that the packaging process for SMT technology requires a great deal of time for process debugging. Thus, how to obtain a stable process is an important task for the packaging process for SMT technology. Based on the past research, it is known that the main reasons for solder defects are the control of the solder-paste printing, the solder quality, the dispensing technique and the dot control technique, which are determined by the accuracy of the component placement, and the stability and reliability of the solder joint structure are determined by the reflow process.
U.S. Pat. No. 6,566,611B2 provides anti-tombstoning structures and methods of manufacture, which reduce asymmetrical and lateral surface-tension forces between devices and a substrate by at least a conducting pad on the patterned substrate. Thereby, the anti-tombstoning due to the asymmetrical and lateral surface-tension forces is not induced during the reflow process. The process of the US patent focused on the stability of the solder joint structure, reducing the tension between the devices and the substrate. However, the US patent did not research the relationship between the glue material and the conducting pads (that is, a conducting structure in the present invention) to further solve problems of adhering accuracy and available yield.
In order to overcome the drawbacks in the prior art, a conducting package structure and a manufacturing method thereof are disclosed. The particular design in the present invention not only solves the problems described above, but is also easy to implement. Thus, the present invention has utility for the industry.